(1) Field of the Invention
The present invention relates to an image processing apparatus used for image filtering processing, an image codec and the like.
(2) Description of the Related Art
With the significant technological progress of digital video equipments in recent years, there are increasing opportunities to perform image processing such as image compression/decompression processing and filtering. In the case of performing such image processing, an image processing apparatus is often used in which processing is divided and the divided processing operations are performed in parallel in a plurality of processing units. However, in the middle of the technological competition, such an image processing apparatus is strictly restricted in terms of processing performance and an amount of memory used, and the image processing is increasing in complexity along with the technological progress.
In the case of parallel operations of the plurality of processing units as described above, conventionally, a CPU controls each of the processing units. The CPU also calculates a parameter necessary for operation of each of the processing units, and set the parameter to each of the processing units. For enhancing the processing performance, interrupt is generated to the CPU upon each processing completion of the processing units, and the CPU subsequently performs parameter setting and making an activation request for a processing unit to be activated next.
The problem here lies in that, since the CPU controls each of the processing units, interrupt is generated to the CPU upon each processing completion of the processing units, which causes deterioration in processing performance in parameter calculation and parameter setting by the CPU. Further, the CPU has a heavy load because of performing processing of parameter calculation, parameter setting, activation order control and synchronous control for each of the processing units, which may slow down the rate of processing performance of the entire system according to that of the CPU.
Further, more parallel operations of the CPU and the processing units are required for improvement in processing performance of the system. However, it is necessary for the CPU and the processing units to operate in synchronization with each other, e.g. the CPU needs to wait for processing completion of the processing unit before performing parameter setting and making an activation request for the processing unit, thereby making it difficult to improve the parallelism.
Further, there are often cases where the processing unit is converted for improving the processing performance of the system or reducing power consumption. In such cases, a CPU program needs to be changed at each change in interface of the processing unit, and hence the compatibility of the CPU program is low. There are also cases where each of the processing units is intended to be operated more parallely for the purpose of improving the processing performance. In such cases, the order of activation of each of the processing units is often intended to be converted based upon a band width of a data transfer bus or performance of each of the processing units. Also in such cases, there is the problem of low compatibility of the CPU program.
In Japanese Patent Laid-Open No. 2003-241983, each of the processing units by itself reads a parameter for next activation from a memory at the time of processing completion of the processing unit, and successively operates based upon the parameter, to reduce a load on the CPU processing. In an apparatus according to Japanese Laid-Open Patent Application No. 2003-241983, parameters are set from a CPU to a memory, and an activation request is made to the processing unit after completion of all the settings. A mechanism for reading a parameter from the memory is present in every processing unit, and the processing unit reads the parameter by itself and successively repeats the processing, Further, the apparatus is provided with a synchronous mechanism where the parameter has a synchronous bit therein and the processing unit is held in a waiting state until processing completion of another processing unit according to the state of the synchronous bit in the parameter.
According to this technique, there is no need for the CPU to perform parameter setting and control on each of the processing units, leading to reduction in load on the CPU.